Building your own RISC-V Processor
Год выпуска: 2020
Производитель: Fedevel
Сайт производителя:
https://fedevel.com
Автор: Steve Hoover
Продолжительность: 4 часа
Тип раздаваемого материала: Видеоурок
Язык: Английский
Описание: Learn to design digital logic for ASICs and FPGAs using next-generation Verilog (Transaction-Level Verilog) design in the online Makerchip IDE. In just a week, you can build and simulate a pipelined RISC-V CPU core from your browser. After this course, you will understand digital logic design concepts and advanced design methods. You'll become familiar with the RISC-V instruction set architecture, and you'll understand how a CPU executes RISC-V instructions to run a computer program.
This course is appropriate for newcomers to digital logic and experts alike. Industry veterans will refresh their toolbox with a fresh perspective on familiar concepts, learning an approach to logic design that has not been possible until recently.
Содержание
lesson-1-combinational-logic.mp4
lesson-2-sequential-logic.mp4
lesson-3-pipelined-logic.mp4
lesson-4-validity-(when-conditions).mp4
lesson-5-risc-v-cpu-preparation.mp4
lesson-6-instruction-fetch-and-decode.mp4
lesson-7-register-file-alu-and-branching.mp4
lesson-8-simple-pipelining-executing-an-instruction-every-three-cycles.mp4
lesson-9-control-and-data-hazard-logic.mp4
lesson-10-data-memory-and-load-and-store-instructions.mp4
Файлы примеров: не предусмотрены
Формат видео: MP4
Видео: Codec: MPEG AAC Audio (mp4a), Video resolution: 1920x1080, Frame rate: 15, ~763 kbps kb/s
Аудио: Codec: H264 - MPEG-4 AVC (part 10) (avc1), Sample rate: 48000 Hz, Channels: Stereo
